/************************************************************\
**	Copyright (c) 2012-2024 Anlogic Inc.
**	All Right Reserved.
\************************************************************/
/************************************************************\
**	Build time: Aug 13 2024 22:21:38
**	TD version	:	5.9.122301
************************************************************/
`timescale 1 ns / 1 ps
module rom
(
  output  [15:0]                doa,
  input   [15:0]                addra,
  input                         clka
);

  rom_9babce99aa75
  #(
      .DATA_WIDTH_A(16),
      .ADDR_WIDTH_A(16),
      .DATA_DEPTH_A(65536),
      .INIT_FILE("../../mif/sine_wave.mif.dat"),
      .FILL_ALL("NONE")
  )rom_9babce99aa75_Inst
  (
      .doa(doa),
      .addra(addra),
      .clka(clka)
  );
endmodule
